- 您现在的位置：买卖IC网 > Sheet目录368 > W9412G6IH-5 (Winbond Electronics)IC DDR-400 SDRAM 128MB 66TSSOPII
W9412G6IH
resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh
operation.
7.8
7.9
Power Down Mode
Two types of Power Down Mode can be performed on the device: Active Standby Power Down
Mode and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers are disabled resulting in
low power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking
CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at
next CLK rising edge. Refer to the diagrams for Power Down Mode.
Input Clock Frequency Change during Precharge Power Down Mode
DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a
minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency
between minimum and maximum operating frequency specified for the particular speed grade.
During an input clock frequency change, CKE must be held LOW. Once the input clock frequency
is changed, a stable clock must be provided to DRAM before precharge power down mode may be
exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS
command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM
is ready to operate with new clock frequency.
7.10 Mode Register Operation
The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all
banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to
A11 and BA0, BA1 address inputs.
The Mode Register designates the operation mode for the read or write cycle. The register is
divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode
selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set
the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode
Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented
the extended function (DLL enable/Disable mode).
The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the
Mode Register Set command must be issued before power operation.
7.10.1 Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2, 4 and 8 words.
A2
0
0
0
0
1
A1
0
0
1
1
x
A0
0
1
0
1
x
BURST LENGTH
Reserved
2 words
4 words
8 words
Reserved
Publication Release Date: Sep. 16, 2009
- 14 -
Revision A06
发布紧急采购，3分钟左右您将得到回复。
相关PDF资料
W9412G6JH-5I
IC DDR SDRAM 128MBIT 66TSOPII
W9425G6EH-5
IC DDR-400 SDRAM 256MB 66TSSOPII
W9425G6JH-5I
IC DDR SDRAM 256MBIT 66TSOPII
W947D2HBJX5E
IC LPDDR SDRAM 128MBIT 90VFBGA
W948D2FBJX5E
IC LPDDR SDRAM 256MBIT 90VFBGA
W949D2CBJX5E
IC LPDDR SDRAM 512MBIT 90VFBGA
W971GG6JB25I
IC DDR2 SDRAM 1GBIT 84WBGA
W971GG8JB-25
IC DDR2 SDRAM 1GBIT 60WBGA
相关代理商/技术参数
W9412G6JH
制造商:WINBOND 制造商全称:Winbond 功能描述:2M ? 4 BANKS ? 16 BITS DDR SDRAM
W9412G6JH-4
制造商:Winbond Electronics Corp 功能描述:8*16B DDR1 制造商:Winbond Electronics Corp 功能描述:IC DDR SDRAM 128M 250MHZ 66TSOP
W9412G6JH-5
制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR SDRAM 128M-Bit 8Mx16 2.5V 66-Pin TSOP 制造商:Winbond Electronics Corp 功能描述:128M BIT DDR1
W9412G6JH-5I
功能描述:IC DDR SDRAM 128MBIT 66TSOPII RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:72 系列:- 格式 - 存储器:RAM 存储器类型:SRAM - 同步 存储容量:4.5M（256K x 18） 速度:133MHz 接口:并联 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 封装/外壳:100-LQFP 供应商设备封装:100-TQFP（14x20） 包装:托盘
W9412G6JH-5TR
制造商:Winbond Electronics Corp 功能描述:128M DDR SDRAM X16 200MHZ, 65N
W942
制造商:Performance Tool 功能描述:6 Piece Hook and Pick Set 制造商:PERFORMANCE TOOLS 功能描述:6 PC HOOK AND PICK SET
W942508BH
制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM
W942508CH
制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM